FPGAtors Update
Workshop #2: SystemVerilog and Vivado Basics
Slides and notes from Workshop #2 on SystemVerilog, testbenches, simulation, and synthesis in Vivado.
Details
Workshop #2 was SystemVerilog and Vivado Basics on September 11 in LAR 234. Lathan led the workshop.
Quick Recap
The workshop walked through a 4-bit ALU, SystemVerilog testbenches, and simulation and synthesis in Vivado.
We used existing code and simulations to follow the ALU from the SystemVerilog source through the testbench and into Vivado.
What We Covered
- SystemVerilog as a hardware description language: modules, input and output ports, logic signals and buses, combinational logic, and selecting operations with an opcode.
- 4-bit ALU: addition, subtraction, a logical left shift, and bitwise inversion.
- Verification basics: driving inputs from a testbench and checking actual results against expected outputs before moving to hardware.
- Vivado simulation: examining how signals change over time.
- Vivado synthesis: seeing how the design becomes a gate-level circuit.
Materials
The workshop used Visual Studio Code and Vivado for the demonstration. The slides cover the ALU operations, code structure, and verification concepts from the workshop.
