Fall 2026 - Ongoing
Guitar Tuner
Intermediate DSP application using Zybo’s on-chip SoC and ADC.
- Project lead
- Lucas
- Hardware / tools
- ZedBoard, Zybo Z7-10, Vitis, Vivado, HLS, RTL, MATLAB / SciPy
- Guitar Tuner = Frequency Detector
- Build FFT in HLS and RTL; compare to MATLAB/SciPy
- Determine speedup, trade-offs, and applications.
- Learn how to interface with GPIO on board, SoC & DSP principles, and have fun with RTL design!
- Members Required: Any
- Roles: None
- Goals: Have fun, make something (even if it’s bad) and gain a better understanding of FFT
Fall 2026 - Ongoing
Ethernet
FPGA-Based Ethernet switch. Initial target is an unmanaged 100 Mb Ethernet Switch.
- Project lead
- Bo
- Hardware / tools
- Ethernet, FPGA, RISC-V, UVM
- FPGA Use Case: Networking!
- Basic unmanaged ethernet switch
- Key Components: Softcore (RISCV) Firmware/PHY, Ethernet MAC, Switching Fabric, Discovery Table
- Verification - UVM
- Design will write plenty of UVM as well!
- Responsible Engineer (RE) for each section
Fall 2026 - Ongoing
RISC-V Processor
Beginner project designing and building a RISCV-based processor core.
- Project lead
- Miguel
- Hardware / tools
- RISC-V, RV64IM, CPU design, Digital logic
- Initial Plan: RV64IM core (64-bit base integer + multiply/divide)
- Classic 5-stage pipeline (IF, ID, EX, MEM, WB)
- Weeks 1-2: teach pipelining concepts, then draft the architecture and design plan
- Get ready to grind
- Be prepared to spend weeks learning foundational concepts/skills before we start with real work
- It’s not about where you start, it’s about where you end up!!!!
